OpenFive and AnalogX announce optimized Chip-to-Chip interface IP solutions

OpenFive along with AnalogX announced a complete sub-system solution and implementation for Chip-to-Chip (C2C) interface with ultra-low latency and power. This solution can be optimized for various bandwidth requirements of AI, HPC, Networking, Storage, Aerospace, and 5G base station applications.

OpenFive’s 8th generation Interlaken Controller IP is silicon-proven on multiple process nodes with tier-1 customers. OpenFive’s 8th gen. Interlaken IP supports from 1 up to 48 SerDes lanes with up to 112G SerDes rates, providing a scalable interface that offers end-to-end reliability using optional re-transmission and flow control mechanisms.

For high-frequency native chip interfaces, OpenFive 8th gen Interlaken has been proven to support up to 1.6Tbps data throughput, and optional forward error correction engines (FEC) further provide bit error rate improvements.

AnalogX USR die-to-die (D2D) SerDes offers sub-pico-joule per bit (pJ/bit) and multi-terabit per mm area efficiency. AnalogX XSR/VSR chip-to-chip SerDes offers a1.5pJ/bit solution for low-energy scaling of multiple SoCs in a single PCB while providing approximately one terabit-per-mm area efficiency.

AnalogX XSR/VSR configurations support up to 20 parallel lanes with very low latency, and AnalogX multi-protocol SerDes offers 2.5 pJ/bit energy efficiency for PCIe Gen 5 connectivity while offering compatibility with CCIX, CXL, and other standard protocols.

AnalogX IPs are currently available across multiple foundries and 22nm, 16nm, 12nm, 7nm, and 6 nm technology nodes.

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